1. Field of the Invention
Embodiments of the invention relate to a semiconductor chip, a film substrate, and a semiconductor chip package using the same. More particularly, embodiments of the invention relate to a chip-on-film semiconductor chip package in which the semiconductor chip is mounted on a film substrate.
2. Description of the Related Art
The complex sequence of fabrication processes used to manufacture semiconductor devices, as well as the technology associated with these processes, may be conceptually divided into the categories of wafer fabrication, packaging, and testing.
Wafer fabrication involves the application of multiple fabrication processes to a wafer serving as a substrate for a plurality of small chips or dies which are formed with identical electrical circuits. When completed, individual dies are fully functional by are not practically accessible to outside circuits and signals.
Testing involves a number of different procedures conducted to ensure the functional performance of each die. Individual test procedures are performed in relation to defined test standards or specifications that effectively separate defective dies from acceptable ones.
Packaging involves a collection of manufacturing processes that separate (e.g., cut) individual dies from a wafer, and then sealed the die in a plastic resin or ceramic before mounting it on a packaging substrate. Packaging allows external circuits and signals to practically interface with a semiconductor die and completes the fabrication of a commercial semiconductor device.
In the context of general packaging technology, various sealing materials have recently been developed as a substitute for the plastic resin or the ceramic. Additionally, various new package types have been developed which allow chips to remain exposed to air without the necessity of sealing them.
As noted above, package facilitates the practical electrical connection of a die with external circuits, provides mechanical and environmental protection, and also aids in the dissipation of heat inevitably generated during the use of the semiconductor device. Conventional techniques for providing an electrical connection to the die include wire bonding, solder bonding, tape automated bonding (TAB), and the like.
The development of contemporary consumer products has motivated improvements in the integration density, data storage capacity and/or operating speed of semiconductor devices. Corresponding demands for packaging technology that allow for dense integration of a semiconductor package having a thin profile and multiple pins has followed.
Various forms of conventional packaging make use of film mounting techniques such as, chip on film (COF) packaging. COF techniques have found particular application in the field of certain semiconductor devices commonly used to drive a display device, such as a Liquid Crystal Display (LCD) panel. Referring to figures (FIGS. 1 and 2, a conventional COF package will now be described in some additional detail.
FIG. 1 is a schematic plan view of a conventional COF semiconductor package 10, and FIG. 2 is a schematic plan view of a semiconductor chip 20 mounted on the COF semiconductor package 10 of FIG. 1.
Referring to FIG. 1, COF semiconductor chip package 10 includes a semiconductor chip 20 and a film substrate 30 on which semiconductor chip 20 is mounted. Semiconductor chip 20 includes a core 25 having integrated circuits (IC), and a periphery 27 having input pads 21 and output pads 23.
Film substrate 30 includes input side copper foil patterns 31 and output side copper foil patterns 33. Input and output pads 21 and 23 of semiconductor chip 20 are electrically connected to corresponding input side and output side copper foil patterns 31 and 33 of film substrate 30 using bump bonding. In this manner, semiconductor chip 20 is mounted on and electrically connected to film substrate 30.
When semiconductor chip package 10 is applied to a display device, input side copper foil patterns 31 and output side copper foil patterns 33 of film substrate 30 are placed between a printed circuit board (PCB) and a display panel so as to be connected to the PCB and the display panel. The number of output pads 23 of semiconductor chip 20 is typically much greater than the number of input pads 21. Accordingly, input pads 21 are successively disposed on an edge of semiconductor 20 close to the PCB. (In the illustrated example, a lower side of semiconductor chip 20 is used as an input side edge).
In contrast, output pads 23 are successively disposed around the remaining edge portion of semiconductor chip 20, particularly the edge portion close to the display panel. (In the illustrated example, an upper side of semiconductor chip is used as an output side edge).
If the required number of output pads cannot be disposed on the output side edge, some of the output pads are disposed on side edges and even the input side edge. The output side copper foil patterns 33 other than those connected to the output pads 23 disposed on the upper side of semiconductor chip 20 must be bent to a certain extent in order to provide the necessary output signals to the attached display. (See, e.g., the output pads disposed at the lower, left and right sides of semiconductor chip 20 having angular or curved portions 33r1, and 33r2).
Potential problems caused by the positioning of the input and output pads on conventional semiconductor chip 20 will now be described with reference to FIG. 2. Referring to FIG. 2, input pads 21 include input pads 21a receiving various input signals, and input pads 21b receiving the power signals required to operate integrated circuits 26 forming semiconductor chip 20. Input pads 21a and 21b and the output pads 23 are electrically connected to integrated circuits 26 through conductive lines. A power supply line 29 communicates power around semiconductor chip 20 and is electrically connected to input pads 21b and integrated circuits 26.
In order to achieve stable and reliable operation of integrated circuits 26, power must be stably supplied. To this end, power supply line 29 must be formed with a sufficiently large physical dimensions (e.g., line width) to properly communicate power along its path (e.g., around the outer circumference of core 25 in the illustrated example). However, expanding the physical size of power supply line 29 and/or extending the length of its path around semiconductor chip 20 will tend to increase the overall size of the chip in order to maintain critical minimum separation distances between various semiconductor chip elements (e.g., the layout separation distance between power supply line 29 and input pads 21a or output pads 23, etc.).